The present invention relates to the fabrication of semiconductor integrated circuits. More particularly, the present invention relates to methods and apparatus for etching through a layer stack of an integrated circuit, including a borophosphosilicate glass (BPSG) layer, during integrated circuit fabrication.
In the fabrication of semiconductor integrated circuits, devices such as component transistors are typically formed on a semiconductor substrate, which may be made of silicon. During the fabrication process, various layers such as BPSG, polysilicon, metal, and the like, may be deposited on the wafer substrate and patterned with a photoresist process. Thereafter, portions of the layers, including the BPSG layer, may be etched away to form interconnect lines, trenches, and other features. The deposition and etching processes may be repeated until the desired circuit is obtained.
To facilitate discussion, FIG. 1 illustrates a cross section view of a pre-etch wafer 100. Wafer 100 is shown having a layer stack 102 disposed above the surface of a substrate 104. An oxide layer 106, typically comprising SiO.sub.2, is shown disposed above silicon substrate 104. Above oxide layer 106, there may be disposed a polysilicon layer 108. A BPSG layer 110, which represents, e.g., a dielectric layer of the wafer stack, may be disposed above polysilicon layer 108.
It should be noted that there may be present other additional layers above, below, or in between the layers shown in layer stack 102. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers. The layers of layer stack 102 are readily recognizable to those skilled in the art and may be formed using any of a number of suitable and known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and a physical vapor deposition (PVD), such as sputtering.
To form the various interconnect lines, trenches and other component regions that may be required in an integrated circuit, portions of certain layers of the layer stack, including, for example, the BPSG layer, may be etched using suitable etchant chemicals. Prior to etching, the wafer is typically prepared using a suitable photoresist technique. By way of example, one such photoresist technique may involve the patterning of the photoresist layer 112 by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching.
To illustrate, there is shown in FIG. 1 masked photoresist regions 112a and 112b, representing regions of photoresist layer 112 that have been left behind following the photoresist patterning step to protect the underlying regions. Areas 118 and 120 represent respectively an unetched contact region and an open field region through which portions of the underlying target layer(s), e.g., layer 110, are exposed for etching.
Once properly masked for etching, the wafer may then be etched using an appropriate etchant. During etching, the areas of the target layer(s) that are left exposed to the etchant, e.g., portions of layer 110 in areas 118 and 120, may be etched away. The areas underlying the protective photoresist mask regions are left behind, forming features which may extend through the etched layer(s).
To achieve greater circuit density, modern integrated circuits are scaled with increasingly narrower design rules. As a result, the feature sizes, for example the width of the contact areas, trenches, and lines, have steadily decreased. By way of example, while a line width of approximately 0.8 microns (.mu.m) may be considered acceptable in a 4 megabit (Mb) dynamic random access memory (DRAM) integrated circuit, 256 Mb DRAM integrated circuits preferably employ interconnect lines as thin as 0.25 .mu.m or even thinner.
As the feature sizes shrink, the process with which the etching step is performed becomes increasingly critical. By way of example, as the features become finer, it becomes increasingly difficult to achieve a uniform etch rate across the wafer. In some cases, the etch rate in the narrow spacings, e.g., area 118, may be slower than that in the wider regions, e.g., area 120. This phenomenon, referred herein as the loading in etch rates, may be a consequence of microloading and aspect ratio-dependent etching (ARDE). Microloading or RIE lag refers primarily to the situation wherein the etch rate is reduced in smaller contacts or trenches when compared to larger contacts or trenches in the same location on the wafer. It can also be said that the aspect ratio of large or small contacts or trenches are different and therefore the etch exhibits ARDE. The loading in etch rates causes trenches to be formed in the layer stack at different rates.
For illustration purposes, FIG. 2 shows a cross-sectional view of post-etch wafer 200, including wafer stack 102 after a conventional BPSG etching step is performed. Even though both areas 118 and 120 were exposed to the same etch chemistries and conditions, the depth of the etch in open field area 120 may extend much further into the underlying polysilicon layer 108 relative to the depth of the etch in the narrow spacing area 118. The difference in etching depths may be caused, in part, by the aforementioned etch rate loading phenomenon.
The loading in etch rates may become more severe when trench widths fall below about 0.5.mu., and especially when trench widths fall below about 0.35.mu.. As a result of the etch rate variations, areas having a higher etch rate, such as open field region 120, may become susceptible to over-etching. As the term is used herein, over-etching is the inadvertent removal of materials from the layer(s) underlying the target layer, e.g., polysilicon layer 108 if BPSG layer 110 is the target layer for the etch. If the etch rate variations are sufficiently large, it may not be possible, for some geometry, to etch through the target layer, e.g., BPSG layer 110, in the narrower spacings without causing undue damage to the underlying layers in open field regions. Such damage may render the wafer undergoing processing unsuitable for use in integrated circuit fabrication. Consequently, the minimization of the etch rate loading may represent an important consideration in the design of a BPSG etch process, particularly in etch processes designed for submicron contact etching.
Another important consideration in the design of a BPSG etch process is the overall BPSG etch rate. In generally, the higher the BPSG etch rate, the greater the throughput, i.e., the higher the number of wafers processed per unit of time. Consequently, all things being equal, a higher BPSG etch rate is generally desirable.
The selectivity of BPSG to other layers during a BPSG etch step may represent another potentially important consideration in the design of a BPSG etch process. As the term is used herein, the selectivity of BPSG to another layer represents the ratio of the etch rate of the BPSG layer relative to the etch rate of the other layer during a BPSG etch. Since a polysilicon layer may be disposed under the BPSG layer in the fabrication of many important electronic devices, e.g., metal oxide semiconductor (MOS) transistors, a high BPSG to polysilicon selectivity is generally desired.
Another potentially important variable may be the profile angle that results from the etch. With reference to FIG. 2, the etch profile angle represents the angle made by the etch sidewall, e.g., the sidewall of BPSG feature 110a for a BPSG etch, to the wafer plane. In general, it is desirable to design an etch process to achieve as vertical an etch profile angle as possible. Still further, uniformity represents another potentially important process result. Uniformity, as the term is used herein, describes how uniform an etch process is across the entire wafer. If the uniformity is poor, some areas of the wafer may be etched severely while other areas may be inadequately etched, possibly rendering some of these areas unsuitable for circuit fabrication. As is apparent, an etch process that can provide a good level of etch uniformity across the wafer surface is highly desirable.
In the prior art, there exist many BPSG etch processes. However, these processes were typically optimized for a particular set of requirements, e.g., high BPSG to titanium silicide or titanium nitride or for different geometries. As technology changes, however, IC chip manufacturers continually search for ways to improve BPSG etch results. In view of the foregoing, what is desired are improved methods and apparatus for etching a BPSG layer in a wafer layer stack.